The output stage of a conventional integrated circuit constituted by MIS-FETs has the structure shown in FIGS. 4 and 5 when it is formed of a silicon gate complementary MOS (hereinafter referred to as silicon gate C-MOS) inverter. Equivalent elements in FIGS. 4 and 5 are designated by the same reference numerals, and the structure illustrated in those drawings is obtained in a manner as follows. That is, boron ions or the like are doped into one of the main surfaces of an N-type semiconductor or substrate 1 at a region thereof in which an N-channel FET is to be formed. Then the substrate is subjected to heat treatment so that a P-well region 3 is formed. Thereafter, an LOCOS (Local Oxidation of Silicon) oxide film 2 is formed through selective oxidization of a region of the substrate other than the region where N-channel and p-channel FETs are to be formed. Then, a gate oxide film 4 is formed on the main surface of the N-type semiconductor substrate 1 in the region where FETs and a polysilicon gate electrode 5 are formed. Using the polysilicon gate electrode 5 and the LOCOS oxide film 2 as a mask, an impurity is doped to form drain and source regions 6a and 7a of the N-channel FET and drain and source regions 6b and 7b of the P-channel FET. Thereafter, a chemical vapor deposition (CVD) oxide film 8 is deposited, the oxide film is removed through photo-etching at portions where contact holes are to be formed, an electrically conductive layer of aluminum or the like is deposited through evaporation over the whole surface, and a wiring pattern is formed through photo-etching to thereby form source electrodes 9a and 9b and a drain electrode 10. Thus, a silicon gate C-MOS inverter as shown in FIGS. 4 and 5 is completed.
In a structure such as the one described above, there are some problems. If the drain electrode 10 is directly connected to a pad electrode in view of the switching speed and the current characteristic, breakdown is apt to occur in the insulator film between the drain regions 6a and 6b and the gate electrode 5. Electric lines of force indicating the electric field concentrate most in junctions between the drain regions 6a and 6b and the P-well region 3 and the substrate 1, respectively, upon external application of a high voltage to the pad electrode due to static electricity.
Accordingly, a device as shown in FIG. 6 has been proposed in which a resistor 14 formed by diffusion or polysilicon is connected between a pad electrode 13 and each of the drain electrodes of P-channel and N-channel FETs 11 and 12 forming a silicon gate C-MOS inverter. A device as shown in FIG. 7 has also been proposed in which a dummy FET circuit 19 constructed by FETs 15 and 16 and resistors 17 and 18 is connected in parallel to the drain electrodes of P-channel and N-channel FETs 11 and 12 forming a silicon gate C-MOS inverter.
In a device having the resistor 14 connected as shown in FIG. 6 there have been problems in reduction of the rising and falling rates of an output signal, generation of oscillation, etc., due to the integration action of the resistor 14 and the output load capacitance. In such a device provided with the dummy FET circuit 19 as shown in FIG. 7, an advantage has been that, since the junction face portion between the substrate and the drain region at the gate side where breakdown may occur is elongated, the breakdown current density at this place can be lowered so that the strength against static electricity can be improved while maintaining predetermined driving capability, but a defect is that the area of the output stage inevitably becomes large.